1. Field of the Invention
The present invention relates to the field of display, and in particular to a structure of active matrix organic light emitting diode (OLED) display (AMOLED) driver circuit with external compensation.
2. The Related Arts
The organic light-emitting diode (OLED) display has the advantages of active light-emitting, low driving voltage, high luminance efficiency, short response time, high clarity and contrast, near 180°, large working temperature range, and ability to realize flexible display and large-area full-color display, and therefore is common considered as the most promising display.
Based on the driving method, OLED display can be categorized as passive matrix OLED display (PMOLED), or active matrix OLED display (AMOLED); that is, the direct addressing and thin film transistor (TFT) addressing, wherein the AMOLED has the pixels arranged in an array, belongs to the active category, has high luminance efficiency, and is often used for high-definition large-area display devices.
The known AMOLED often suffers the problems of un-even luminance among pixels and un-even ageing among the TFTs and the OLED of each pixel, and thus certain compensation is required. FIG. 1 is a schematic view showing a conventional structure of AMOLED driver circuit with external compensation, comprising a plurality of pixel unit circuit 10 arranged in an array, a source driver module 40 and a detection module 50 electrically connecting each row of the pixel unit circuits 10, and a gate scan driver module 30 and a detection scan driver module 20, electrically connecting each column of the pixel unit circuits 10. The gate scan driver module 30 and the detection scan driver module 20 are mutually independent. The detection scan driver module 20 comprises a plurality of cascade first shift register units, having the same number as the number of the rows of the pixel unit circuits. The gate scan driver module 30 comprises a plurality of cascade second shift register units, having the same number as the number of the columns of the pixel unit circuits.
Refer to FIG. 1 and FIG. 2. Each pixel unit circuit 10 comprises a first TFT T10, a second TFT T20, a third TFT T30, and an OLED D1. The gate of the first TFT T10 is connected to a gate scan signal G(n) provided by the gate scan driver module 30 to the corresponding column of the pixel unit circuits where the pixel unit circuit 10 belonging to, and the source is connected to a data signal Vdata provided by the source driver module 40 to the corresponding row of the pixel unit circuits where the pixel unit circuit 10 belonging to; the gate of the second TFT T20 is connected to the drain of the first TFT T10, and the drain is connected to a high level power source ELVDD; the gate of the third TFT T30 is connected to a detection scan driver signal G(n)S provided by the detection scan driver module 20 to the corresponding column of the pixel unit circuits where the pixel unit circuit 10 belonging to, the source is connected to the source of the second TFT T20, and the drain is connected to the detection module 50 through corresponding routing of the row of the pixel unit circuits where the pixel unit circuit 10 belonging to; and the anode of the OLED D1 is connected to the source of the second TFT T20 and the cathode is connected to a low level power source ELVSS.
In the above structure for the known AMOLED driver circuit with external compensation, the first TFT T10 and the third TFT T30 of each column of the pixel unit circuits 10 are controlled respectively by the gate scan driver module 30 and the detection scan driver module 20. To perform TFT or OLED detection under the normal display condition, the detection is often performed during the V-blanking of each frame to avoid affecting the normal display frame. However, during V-blanking, because the gate scan driver signal and the detection scan driver signal outputted respectively by the gate scan driver module 30 and the detection scan driver module 20 are transmitted stage-by-stage from the first stage, the gate scan driver module 30 and the detection scan driver module 20 cannot assign directly which column of pixel unit circuits to be activated. For example, to perform detection on the last column of the pixel unit circuits, the detection can not be performed until the gate scan driver signal and the detection scan driver signal outputted respectively by the gate scan driver module 30 and the detection scan driver module 20 reach the last column of the pixel unit circuits. As shown in FIG. 2, the detection circuit in the detection module 50 corresponding to each pixel unit circuit is usually an integrator 70, the time required to perform signal integral computing and data processing is longer. Because the V-blanking time is limited, the above detection process is unable to be performed within such short time.